Product Overview

The DW3000 IC family is a fully integrated single chip Ultra Wideband (UWB) low-power low-cost transceiver IC compliant to IEEE802.15.4- 2015 and IEEE802.15.4z (BPRF mode). It can be used in 2-way ranging, TDoA and PDoA systems to locate assets to an accuracy of 10 cm.

DW3000

UWB Transceiver

Key Features

• IEEE802.15.4-2015 UWB IEEE802.15.4z (BPRF mode)
• Supports channels 5 & 9 (6489.6 MHz & 7987.2 MHz)
• Supports 2-way ranging, TDoA and PDoA location schemes
• Low external component count
• Supports enhanced Time-of-Flight security modes
• Integrated HW AES 256
• Worldwide UWB Radio Regulatory compliance
• Low power consumption
• Data rates of 850 kbps and 6.8 Mbps
• Packet length up to 1023 bytes
• Integrated MAC support features
• Up to 36 MHz SPI interface
• QFN40 (5mm x 5 mm) and WLCSP52 (3.1mm x 3.5mm) package options

Key Benefits

• Provides precision location and data transfer simultaneously
• Asset location to an accuracy of 10 cm
• High multipath fading immunity
• Secure ranging/distance measurement
• Supports high tag densities in RTLS
• Low-cost precision location
• Suitable for coin cell applications

Applications

• Precision real time location systems (RTLS) using two-way ranging, TDoA or PDoA schemes in a variety of markets:
  • o Healthcare
  • o Consumer
  • o Industrial
• Presence detection for secure entry and secure payment
• Location aware wireless sensor networks

Table of Contents

List of Figures

List of Tables

DOCUMENT INFORMATION

Disclaimer

Decawave reserves the right to change product specifications without notice. As far as possible changes to functionality and specifications will be issued in product specific errata sheets or in new versions of this document. Customers are advised to check with Decawave for the most recent updates on this product.

Copyright © 2020 Decawave Ltd

LIFE SUPPORT POLICY

Decawave products are not authorized for use in safety-critical applications (such as life support) where a failure of the Decawave product would reasonably be expected to cause severe personal injury or death. Decawave customers using or selling Decawave products in such a manner do so entirely at their own risk and agree to fully indemnify Decawave and its representatives against any damages arising out of the use of Decawave products in such safety-critical applications.

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

REGULATORY APPROVALS

The DW3000, as supplied from Decawave, has not been certified for use in any particular geographic region by the appropriate regulatory body governing radio emissions in that region although it is capable of such certification depending on the region and the manner in which it is used.

All products developed by the user incorporating the DW3000 must be approved by the relevant authority governing radio emissions in any given jurisdiction prior to the marketing or sale of such products in that jurisdiction and user bears all responsibility for obtaining such approval as needed from the appropriate authorities.

TRADEMARKS

FiRa, FiRa Consortium, the FiRa logo, the FiRa Certified logo, and FiRa tagline are trademarks or registered trademarks of FiRa Consortium or its licensor(s)/ supplier(s) in the US and other countries and may not be used without permission. All other trademarks, service marks, and product or service names are trademarks or registered trademarks of their respective owners.

1 IC DESCRIPTION

DW3000 is a fully integrated low-power, single chip CMOS RF 6.5GHz-8GHz IR-UWB transceiver IC compliant with the IEEE 802.15.4-2015 (HRP UWB PHY), IEEE 802.15.4z and IEEE 802.15.8 standards.

DW3000 consists of an analog front end containing a receiver and a transmitter and a digital back end that interfaces to an off-chip host processor. A TX/RX switch is used to connect the receiver or transmitter to the antenna port. Temperature and voltage monitors are provided on-chip.

The receiver consists of an RF front end which amplifies the received signal in a low-noise amplifier before downconverting it directly to baseband. The receiver is optimized for wide bandwidth, high linearity and low noise figure. This allows each of the supported IEEE802.15.4-2015 UWB channels to be down converted with minimum additional noise and distortion. The baseband signal is demodulated and the resulting received data is made available to the host controller via SPI.

The transmit pulse train is generated by applying digitally encoded transmit data to the analog pulse generator. The pulse train is up-converted to a carrier generated by the synthesizer and centred on one of the permitted IEEE802.15.4-2015 UWB channels. The modulated RF waveform is amplified before transmission from the external antenna.

A variant of the IC is available which has two RF antenna ports and is used for Phase Difference of Arrival (PDoA) applications. In this variant the receiver switches between antenna ports to enable a PDoA measurement.

The IC has an on-chip One-Time Programmable (OTP) memory. This memory can be used to store calibration data such as TX power level and crystal initial frequency error adjustment.

Figure 1: IC Block Diagram

The Always-On (AON) memory is 256 bytes and can be used to retain DW3000 configuration data during the lowest power operational states. The AON can operate directly from battery. This data is downloaded during crystal start up automatically.

DW3000 contains a phase-locked-loop (PLL) with integrated loop filters. This PLL provides the RF local oscillator signals for the Rx Mixer and the Tx RF frequency carrier to the Tx mixer. The channel information signal defines the output channel frequency as follows; channel 5 = 6489.6 MHz, channel 9 = 7987.2 MHz

The DW3000 has various debug and test options (RF loopback, event counters. test modes and more) and gives access to internal signals for on-the-bench debugging and to simplify production test.

The DW3000 incorporates Time Stamp system security features to prevent all known hacking type attacks such as 'imposter', 'cicada', 'parasite' 'record & replay' attacks etc.

The host interface includes a peripheral-only SPI for device communications and configuration. Several MAC features are implemented including CRC generation, CRC checking and receive frame filtering.

1.1 DW3000 Variants

The following DW3000 variants exists:

Table 1: DW3000 variants

1.2 DW3000 Backwards compatibility with DW1000

DW3000 is backward compatible with DW1000 on channel 5 and for data rates of 6.8 Mb/s and 850 kb/s.

2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

The DW3000 chip can be supplied in two packages, QFN (40 pads) or WLSCP (52 balls). The pin assignments for packages is illustrated in Figure 2 and Figure 3 and the description is given in Table 2 below.

Figure 2: The QFN Top view pin assignments

Table 2: DW3000 QFN & WLCSP Pin functions

1 Reference to the schematics and the layout. 2 GPIO pins are not suitable to drive LEDs directly. See Table 5 for details of the maximum current limit.

Table 3: Abbreviations

3 ELECTRICAL SPECIFICATIONS

3.1 Nominal Operating Conditions

Table 4: Nominal Operating Conditions

Note: Unit operation is guaranteed by design when operating within these ranges. Sufficient headroom for any power supply voltage ripple should be considered in system designs.

3.2 DC Characteristics

Tamb = 25 ˚C, all supplies at 3.0 V.

Table 5: DC Characteristics

1 Note: Maximum power values are 1.4dB lower for Channel 9 and 1.2dB lower for Channel 5 for PDoA variants because of the additional loss of the PDoA switch.

Note: Power consumption can be significantly reduced if VDD3 is supplied from a high efficiency SMPS at 1.6V for example.

3.3 Receiver AC Characteristics

Table 6: Receiver AC Characteristics

3.4 Receiver Sensitivity Characteristics

The receiver sensitivity measured at 1% Packet Error Rate (PER).

Table 7 Test conditions of the Rx sensitivity measurements

Table 8: Rx Sensitivity Characteristics (Channel 5)

Table 9: Rx Sensitivity Characteristics (Channel 9)

Note: The above typical receiver sensitivities are for DW3110 and DW3210 variants. For PDoA variants (DW3120, DW3220) the RX sensitivity level is approximately 1.4 dB worse for Channel 9 and 1.2 dB worse for Channel 5 (i.e. less sensitive) due to the additional internal PDoA switch.

3.5 Reference Clock AC Characteristics

Tamb = 25 ˚C, all supplies at 3.0 V.

Table 10: Reference Clock AC Characteristics

1Note: Chip start-up time depends on this clock. The typical frequency of Slow LP OCS reflected the chip start-up time of 913 us. With the time required to download the AON after wake-up, the overall start-up time is ~1000 us. It is possible to trim the LP OSC to the higher frequency in software, which would decrease the start-up time to ~770us.

3.6 Transmitter AC Characteristics

Tamb = 25 ˚C, all supplies at 3.0 V.

1 The TX power quoted is for the DW3110 (CSP) variant, measured as a mean power in a 1 MHz bandwidth. Typically the QFN package variants (DW3210, DW3220) output 2 dB less maximum TX power. For the PDoA variants (DW3120, DW3220) the TX power is reduced by an additional 1.2 dB for Channel 5 and 1.4 dB for Channel 9 due to insertion loss associated with the internal PDoA switch.

3.7 Link Budget

Using the receiver sensitivity above, expected transmission link budgets can be estimated with the following assumptions:

• 1. Receiver sensitivities as per Receiver Sensitivity section.
• 2. Transmitter and receiver antennas have 0 dBi gain.
• 3. No losses between the antenna and DW3000 RF pins.
• 4. The transmitter is operating at an EIRP of -41.3 dBm/MHz (widely used regulatory limit).

Table 12: Typical Link Budget for DW3110

3.8 Temperature and Voltage Monitor Characteristics

Table 13: Temperature and Voltage Monitor Characteristics

3.9 Location functionality Characteristics

Table 14: Location Accuracy Characteristics

1 After calibration is applied. Approximately +/-15cm without calibration.

2 Ranging standard deviation is measured at -85 dBm power level and with DS-TWR. 3 Note: In a typical PDoA based system, the computed angle of arrival (AoA) accuracy is better than the PDoA accuracy

by a factor of approximately two i.e. if PDoA accuracy is ±10° then AoA accuracy is ±5°. 4 For optimal PDoA performance, a carrier frequency offset of greater than |5| ppm is required between devices.

⁵ For best PDoA standard deviation, use PLEN 128 and STSLEN 256.

3.10 Absolute Maximum Ratings

Table 15: Absolute Maximum Ratings

1 Note: Tested according JEDEC-JSTD-020 spec.

3.11 Typical performance

3.11.1 Transmit Spectrum

The typical transmit spectrums for channel 5 and channel 9 are on the pictures below.

• The UWB configuration is:
  • PRF = 64 MHz
  • Preamble length = 64 symbols
  • STS length = 64 symbols
  • Data length = 20 bytes

Figure 4: Typical Transmit Spectrum Channel 5

Figure 5: Typical Transmit Spectrum Channel 9

3.11.2 Transmit Power Adjustment

DW3000 has a coarse TX power adjustment and a fine TX power adjustment. The plots below show the relationship between these adjustments for each channel. The y-axis, Power (dB), is the output power in dB below the maximum.

Figure 6 Tx power coarse and fine gain settings - Channel 5

Figure 7 Tx power coarse and fine gain settings - Channel 9

3.11.3 Receiver Blocking

The following plots show typical blocking levels to give 1% UWB PER at 3 dB back off from the sensitivity point. The UWB configuration is:

• PRF = 64 MHz
• Preamble length = 64 symbols
• STS length = 64 symbols

Figure 8 Blocking performance - Channel 5

Figure 9 Blocking performance - Channel 9

3.11.4 Ranging

Typical measured distribution of double-sided two-way ranging (DSR) performance.

Figure 10 Ranging performance - Channel 5

Figure 11 Ranging performance - Channel 9

4 FUNCTIONAL DESCRIPTION

4.1 Physical Layer Modes

Please refer to IEEE802.15.4-2015 and IEEE802.15.4z for the PHY specification.

4.2 Supported Channels and Bandwidths

The DW3000 supports the following IEEE802.15.4-2015 and IEEE802.15.4z UWB channels:

Table 16 UWB Channels supported

4.3 Supported Bit Rates and Pulse Repetition Frequencies (PRF)

The DW3000 supports IEEE802.15.4-2011, IEEE802.15.4-2015 UWB standard bit rates 850 kbps and 6.81 Mbps and nominal PRF values of 16 MHz and 64 MHz. The Base PRF (BPRF) mode of a newly defined draft standard IEEE802.15.4z is also supported.

Table 17 PRF and data rates supported

Actual PRF mean values are slightly higher for SHR as opposed to the other portions of a frame. Mean PRF values are 16.1/15.6 MHz and 62.89/62.4 MHz, nominally referred to as 16 MHz and 64 MHz in this document. Refer to [1], [2] (UWB PHY rate-dependent and timing-related parameters) for full details of peak and mean PRFs.

1 Backward-compatible for 802.15.4-2011 UWB devices

² Base PRF (BPRF) mode of 802.15.4z(draft) and 802.15.4-2011

In general, lower data rates give increased receiver sensitivity, increased link margin and longer range but due to longer frame lengths for a given number of data bytes they result in increased air occupancy per frame and a reduction in the number of individual transmissions that can take place per unit time. 16MHz PRF gives a marginal reduction in transmitter power consumption over 64 MHz PRF (BPRF).

4.4 Symbol timings

Timing durations in IEEE802.15.4 are expressed in an integer number of symbols. This convention is adopted in DW3000 documentation. Symbol times vary depending on the data rate and PRF configuration of the device and the part of the frame. DW3000 can transmit PHR on the 0.85 and 6.81 Mbps data rates. See the table below for symbol timings supported by DW3000.

Table 18 DW3000 Symbol Timings Duration

4.5 Frame Format IEEE802.15.4-2011, IEEE802.15.4-2015

IEEE802.15.4-2011, IEEE802.15.4-2015 frames are structured as shown in Figure 12. Detailed descriptions of the frame format are given in the standard. The frame consists of a synchronisation header (SHR) which includes the preamble symbols and start frame delimiter (SFD), followed by the PHY header (PHR) and data. The data frame is usually specified in number of bytes and the frame format will include 48 Reed-Solomon parity bits following each block of 330 data bits (or less).

While zero length payloads and zero length PHR is supported the maximum frame length is 1023 bytes, including the 2-byte FCS.

Figure 12: IEEE802.15.4-2011 PPDU Structure

4.6 Packet Formats of IEEE Std 802.15.4z™

The 4z amendment added new packet formats to HRP UWB PHY incorporating a Scrambled Timestamp Sequence (STS) into the packet structure, defining four STS Packet Configurations as shown in Figure 7 below.

The STS is a random sequence of positive and negative pulses generated using an AES-128 based deterministic random bit generator (DRBG). Only valid transmitters and receivers have the correct seed (i.e., the key and IV) to generate the sequence for transmission and to validly cross correlate in the receiver to determine the receive timestamp. The STS provides for secure receive timestamping and secure ranging.

4.7 Proprietary long frames

The DW3000 offers a proprietary long frame mode where frames of up to 1023 bytes may be transferred. Refer to the DW3000 user manual for full details.

4.8 No Data frames

The DW3000 offers zero length payloads and zero length PHR (SP3). This is for use cases where an alternative method of data communications is available.

4.9 Host Controller Interface

The primary interface DW3000 is via a 4 wire SPI interface. DW3000 will act a SPI peripheral device, in nondaisy-chain mode and operate at SPI clock frequencies up to 36MHz.

4.9.1 SPI Functional Description

The host interface to DW3000 is a 4-wire SPI-compatible peripheral. The assertion of SPICSn low by the SPI controller (host) indicates the beginning of a transaction.

The SPI interface is used to read and write registers in the DW3000 device. All data and address transfer on the SPI is most significant bit first. All address bytes are transmitted with MSB first, and all data is transmitted commencing with lowest addressed byte.

• Assertion low of SPICSn initialises transaction.
• De-assertion high of SPICSn ends the SPI transaction.
• The device supports direct and per-byte sub-addressing access to the full register space.
• Efficient block data reading/writing is allowed. Continuous, long transactions can be carried out while the addressed location is auto-incremented on the DW3000 side.

The SPICDO (ex. SPIMISO) I/O of DW3000 is going open-drain when SPICSn is de-asserted, to allow interoperation with other peripherals on the SPI bus.

SPI daisy chaining is not supported. This is the mode where the CDO (ex. SPIMISO), CDI (ex. SPIMOSI) lines are passed through a device when it is not chip selected.

4.9.2 SPI Timing Parameters

SPIMOSI

t1

The SPI peripheral complies with the Motorola SPI protocol within the constraints of the timing parameters listed i n Table 19 and illustrated in Figure 13 and Figure 14.

Figure 13: SPI Timing Diagram

t4

t3

7 6 5

t2

Table 19 SPI Timing Parameters

1Note: SPICLK frequency in CRC mode is 20MHz.

4.9.3 SPI Operating Modes

The SPI interface supports both clock polarities (SPIPOL=0/1) and phases (SPIPHA=0/1), as defined in the Motorola SPI protocol. The DW3000 transfer protocols for each SPIPOL and SPIPHA setting are given in Figure 14 and Figure 15. These modes are selected using GPIO 5 & 6 as follows:

Table 20 SPI Mode Configuration

GPIO 5 and 6 pins are sampled as shown i n Figure 21 an d Figure 22 to determine the SPI mode. They are internally pulled low to configure a default SPI mode 0. If mode other than 0 is required, then they should be pulled up using an external resistor of value no greater than 10 kΩ to the VIO_D supply.

Figure 14: DW3000 SPIPHA=0 Transfer Protocol

Figure 15: DW3000 SPIPHA=1 Transfer Protocol

4.9.4 SPI Transaction Formatting

The SPI command structure allows for 4 different types of SPI command:

• 1. Fast, single byte commands. Up to 32 unique commands such as "TX now", "TX/RX Off".
• 2. Fast addressed mode. Allowing for read and write addressing to 32 addresses. This command structure is padded by a trailing bit to allow the SPI address decoder time to fetch any read data. The length of the read is determined by the length of the SPI transaction.
• 3. Full addressed mode. Allowing for read and write addressing to 32 addresses and up to 128 byte offset addressing. This command structure is padded by a trailing bit to allow the SPI address decoder time to fetch any read data. The length of the read or write is determined by the length of the SPI transaction.
• 4. Masked write transaction. These are intended to simplify read-modify-write operations by allowing the host to write to an address and apply a set, clear or toggle mask to 1, 2, or 4 bytes. The SPI command decoder then carries out the required read-modify-write instructions internally.

Figure 16: SPI Command Formatting

4.9.5 GPIO and SPI I/O internal pull up/down

All of the GPIO pins have a software controllable internal pull-down resistor except for SPICSn, which has a pullup, to ensure safe operation when input pins are not driven. The value of the internal resistors can vary with the VDD1 supply voltage over a range from 10 kΩ (VDD1 is 1.8V) to 30 kΩ (VDD1 is 3.6V).

Figure 17: SPI and GPIO pull up/down

4.10 Reference Crystal Oscillator

With the addition of an external 38.4 MHz crystal and appropriate loading capacitors, the on-chip crystal oscillator generates the reference frequency for the integrated frequency synthesizer's RFPLL.

The DW3000 crystal oscillator is used to provide the reference clock to the internal PLL and provides a direct clock source to the digital core when operating in the lower power INIT_RC mode. The oscillator operates at a frequency of 38.4 MHz. A trim facility is provided which can be used to trim out crystal initial frequency error. Typically, a trimming range of ± 20 ppm is possible using a 6-bit trim range. This trimming in 0.125pF steps provides for up to 8 pF additional capacitance on the XTI and XTO crystal connections.

4.10.1 Calculation of external capacitor values for frequency trim

Ideally the value of external loading capacitors (Cext) should be calculated to give an equal trim range about the center trim value. To do this, one needs to estimate the parasitic capacitance (Cpar) between the crystal pads XTI/XTO and the crystal pads. A good starting estimate is usually about 3.3 pF however some trial and error maybe required initially. The values of Cm, Lm, Rm and Co obtained from the crystal manufacturer are also required.

Figure 18 Crystal Model

Using the following formulae, the required Cext and trim range can be estimated where:

fs = series frequency fp = parallel frequency fl = loaded (desired) frequency

$$f\_s\; =\; \backslash frac\{1\}\{2\backslash pi\backslash sqrt\{C\_M\; L\_M\}\}$$
$$f\_P\; =\; f\_s\; \backslash left(\; \backslash sqrt\{1\; +\; \backslash frac\{C\_M\}\{C\_0\}\}\; \backslash right)$$
$$f\_L\; =\; f\_s\; \backslash left(\; \backslash sqrt\{1\; +\; \backslash frac\{C\_M\}\{C\_L\}\}\; \backslash right)$$
$$C\_L\; =\; C\_0\; +\; \backslash frac\{1\}\{2\}\; \backslash left(\; C\_\{TRIM\}\; +\; C\_\{PAR\}\; +\; C\_\{EXT\}\; \backslash right)$$
$$\backslash Delta\; f\_\{ppm\}\; =\; 10^6\; \backslash times\; \backslash frac\{f\_L\; -\; f\_\{L\_\{XOM\}\}\}\{f\_\{L\_\{XOM\}\}\}$$

A typical crystal trimming plot is shown below:

Figure 19 Crystal Trim plot

5 OPERATIONAL STATES

5.1 Overview

DW3000 has a number of basic operations states as described in Table 21.

Table 21: Operating States

5.2 Operating State Transitions

Figure 20: Operating State Transitions

6 POWERING DW3000

DW3000 is designed such that it can be powered in a number of different configurations depending on the application. These options are described below. Figure 21: Timing diagram for cold start POR details the power up sequence when external power sources are applied. The power supply design should ensure that VDD2a/b and VDD3 are stable less than 10ms after VDD1 (3.3V) comes up, otherwise a device reset is required.

When the external power source is applied to the DW3000 for the first time (cold power up), the internal Power On Reset (POR) circuit compares the externally applied supply voltage (VDD1) to an internal power-on threshold (approximately 1.5V), and once this threshold is passed the AON block is released from reset and the external device enable pin EXTON is asserted.

Then the VDD2a and VDD3 supplies are monitored and once they are above the required voltage as specified in the datasheet (2.2V and 1.4V respectively), the fast RC oscillator (FAST_RC) and crystal (XTAL Oscillator) will come on within 500 µs and 1 ms respectively.

The DW3000 digital core will be held in reset until the crystal oscillator is stable. Once the digital reset is deasserted the digital core wakes up and enters the INIT_RC state, (see Figure 21 and Figure 22). Then once the configurations stored in AON and OTP have been restored (into the configuration registers) the device will enter IDLE_RC. Then the host can set the AINIT2IDLE configuration bit in SEQ_CTRL and the IC will enable the CLKPLL and wait for it to lock before entering the IDLE_PLL state.

Figure 21: Timing diagram for cold start POR

Figure 22 Timing diagram for warm start

6.1 Lowest Bill of Materials (BOM) powering scheme

In the following configuration the DW3000 is powered directly from a coin-cell battery. This is for applications that require the minimal BOM. The bulk capacitor required to store energy. The value of capacitor depends on the time the transceiver is in the active Tx/Rx state, typically 47uF.

Figure 23: Lowest BOM powering option

6.2 Highest Efficiency powering scheme

In the following configuration the external Buck SMPS regulator is used. This is for applications that require the longest battery lifetimes. Depending on the use-case either the EXTON output or MCU can be used to control the Buck DC-DC.

Figure 24: Single O/P Buck SMPS option

6.3 Mobile powering scheme

In the following configuration the external PMIC circuit is used to provide all the power rails to the chip. The VDD1 is used to power Always-On memory and IO rail only, the current consumption for powering AON is negligible.

Figure 25: Mobile Option

6.4 Typical power profiles

The current drawn during operation with DW3000 will vary depending on supplies voltage used, batteries used, use case etc. Figure 26 shows the current drawn from a battery with typical TX frames transmitted. Figure 28 shows the current drawn for the reception of the frame by the receiver.

6.4.1 TX current profile for the minimal BOM

Figure 26 below shows the current profiles during of frame transmission without secure preamble and 6.8Mbps TDoA tag frame. This mode is compatible to a DW1000 TDoA tag blink. All supplies are connected to the battery assumed to at 3.0V, i.e. the lowest BOM option, see sectio n 6.1.

Figure 26: Current profile when transmitting a frame (6.8Mbps) in lowest BOM use case

6.4.2 TX current profile for high efficiency modes

In the high efficiency modes, i.e. when an external DC-DC/PMIC is used, the current consumption from VDD3 (1.6V) and VDD2a and VDD2b (2.5V) are different, therefore more efficient current consumption can be achieved using alternative powering schemes, illustrated in sectio n 6.2 a nd 6.3. The VDD1 is used to power AON memory and IO rail only, the current consumption for powering AON is negligible.

For high efficiency schemes, the overall power consumption depends on the efficiency of external DC-DC and/or PMIC. For DW3000 device, the power consumption during different phases of operation as illustrated below.

Figure 27: Current consumption during TX for high efficiency powering modes

6.4.3 RX current profile

Figure 28 illustrates the current profiles during the reception of a single frame. All supplies are connected to the battery assumed to at 3.0V, i.e. the lowest BOM option, see 6.1.

The example given for a case where a variable part of Preamble Hunt is ~30us. The preamble hunt can be minimized to 0 (zero) when using Delayed RX in the optimized Two Way Ranging (TWR) protocol (not illustrated), however with a Delayed RX the IDLE PLL should be maintained in between end of the transmission and start of the reception.

Figure 28: Current profile for receiving a frame

6.4.4 RX current profile for high efficiency BOMs

In the high efficiency modes, i.e. when an external DC-DC/PMIC is used, the current consumption from VDD2 (2.5V) and VDD3 (1.6V) are different, therefore more efficient current consumption can be achieved using alternative powering schemes, illustrated in section 6.2 and 6.3. The VDD1 is used to power AON memory and IO only, the current consumption for powering AON is negligible.

For high efficiency schemes, the overall power consumption depends on the efficiency of external the DC-DC and/or PMIC. For the DW3000 device, the power consumption during different phases of operation as illustrated below.

Figure 29: Current consumption during RX for high efficiency powering modes

6.4.5 Typical TWR current profile

Figure 30 illustrates the current profiles of the Initiator device during the typical optimized Double Sided TWR scheme. All supplies are connected to the battery assumed to at 3.0V, i.e. the lowest BOM option, see 6.1.

The example given for a case with Delayed RX and TX are used in the optimized TWR protocol. It should be noted, that IDLE PLL should be maintained in between TX and RX frames that chip clock domain is stable during the Two Way Ranging. If chip is used for protocols, where its precise clock is not needed (for example for application with Data transfer), then IDLE RC can be used to save power between TX and RX states. In this case the PLL Lock time should be considered before start of TX and RX.

Figure 30 Current profile of Initiator in the DS-TWR with embedded data to frames

6.5 Internal Power supply distribution

The block diagram shows the power distribution within the DW3000 device.

Figure 31: Internal power distribution

7 APPLICATION INFORMATION

7.1 Application Circuit Diagram (lowest BOM powering scheme)

Figure 32: DW3000 WLCSP Application Circuit

Note : The suggested crystal loading will vary depending on board layout and actual crystal used. BPF on pins RF1/RF2 may be required for certification in some regions that mandate conducted testing.

7.2 Boost Circuit Diagram

To power DW3000 from a low-capacity battery, it is recommended to use the boost circuit shown on the picture below.

7.3 Recommended chip layout and Stack-up

The recommendation for the chip layout:

• Keep all the traces as short as possible.
• Avoid mixing Analog (RF1, RF2, XIN, XOUT), Power (VDD1, VDD2a/b, VDD3, VDD decoupling) and Digital (SPI etc) groups together.
• Place all the decoupling capacitors as close to the corresponding chip pads as possible, the smaller capacitor should be closer to the pad. Connect ground pad of each capacitor to the good ground plane directly to minimize ESR and ESL of the return current path.
• RF1 and RF2 lines should be 50 Ohm impedance-controlled lines. The DC-blocking 2 pF capacitor pads should be embedded into the track (have the same width) to remove any possible discontinuities.
• The ground copper should be removed from under the chip in the areas shown in the picture (Top layer and Inner Layer 1). The first solid ground copper should be on the Inner Layer 2. If different stack-up will be used – this first solid copper layer should be at least 0.25 mm away from the Top Layer, any inner layers close to the Top Layer should have the ground removed in the same manner as in Inner Layer 1 above.

7.3.1 WLCSP variant Stack-up

The DW31x0 WLCSP stack-up recommendation is shown below.

7.3.2 QFN variant Stack-up

The DW32x0 QFN stack-up recommendation is shown below.

Figure 35 Recommended QFN Stack-up

7.4 Recommended Components

The list of components tested and approved by Decawave are shown in the table below. The use of DC-DC regulators and TCXO's is optional.

Table 22 Recommended Components

8 REFLOW PROFILES

8.1 Reflow profile of the WLCSP package

The DW31x0 should be soldered using the reflow profile specified below.

Table 23 Critical Parameters for Lead Free Solder of the WLSCP package

8.2 Reflow profile of the QFN package

The DW32x0 should be soldered using the reflow profile specified in JEDEC J-STD-020 as adapted for the particular PCB onto which the IC is being soldered.

9 PACKAGING & ORDERING INFORMATION

9.1 Package Dimensions WLCSP

Figure 37: Package Dimensions WLCSP

9.2 QFN chip variant

Figure 38: Package Dimensions QFN

9.2.2 Tape and Reel packaging information: QFN chip variant

Tape orientation and dimensions:

Figure 39 QFN Tape Orientation and Dimensions

REEL INFORMATION : 330mm REEL (13")

Base material: High Impact Polystyrene with Integrated Antistatic Additive. Surface resistivity: Antistatic with surface resistivity less than 1 x 10e12ohms per square.

Figure 40 QFN Reel Information

All dimensions and tolerances are fully compliant with EIA 481-C and are specified in millimeters (mm). Quantity per reel = 4000 units.

9.2.3 Tape and Reel packaging information: WLCSP chip variant

Tape orientation and dimensions:

Figure 41 WLCSP Tape Orientation and Dimensions

REEL INFORMATION : 330mm REEL (13")

Figure 42 WLCSP Reel Information

9.2.4 WLCSP, QFN Device Package Marking

The diagrams below shows the package markings for DW3210, DW3220, DW3110 and DW3120.

Legend:

DW3xx0 Part number XXXXXXXX Lot number

ZZYYWW Assembly site ID (ZZ), A2 for QFN B2 for WLCSP Year (YY) and Week (WW) number

Figure 43: Original Device Package Markings

Figure 44. New Device Package Markings (after PCN 2026)

10 GLOSSARY

Table 24: Glossary of Terms

11 REFERENCES

[1] IEEE802.15.4-2011 or "IEEE Std 802.15.4™‐2011" (Revision of IEEE Std 802.15.4-2006). IEEE Standard for Local and metropolitan area networks – Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs). IEEE Computer Society Sponsored by the LAN/MAN Standards Committee. Available from http://standards.ieee.org/

[2] IEEE802.15.4-2015 or "IEEE Std 802.15.4™‐2015" (Revision of IEEE Std 802.15.4-2011). IEEE Standard for Local and metropolitan area networks – Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs). IEEE Computer Society Sponsored by the LAN/MAN Standards Committee. Available from http://standards.ieee.org/

12 DOCUMENT HISTORY

Table 25: Document History

13 FURTHER INFORMATION

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